The present invention relates to an active matrix liquid crystal display (hereinafter referred to as AMLCD) in which a thin film transistor (hereinafter referred to as TFT) array substrate in which TFTs are provided as switching elements is provided and to a method of manufacturing TFT array substrate for AMLCD.
FIG. 18 is a diagram of an equivalent circuit of the AMLCD, and FIG. 19 is a diagram of equivalent circuit of one pixel of the AMLCD.
In FIGS. 18 and 19, reference numeral 21 denotes a TFT, reference numeral 2 denotes a gate line (gate electrode line), reference numeral 9 denotes a source line (source electrode line), reference numeral 22 denotes a pixel capacitance provided by a liquid crystal material in the equivalent circuit (hereinafter reference numeral 22 denotes directly liquid crystal display), reference numeral 23 denotes a storage capacitance, reference numeral 4 denotes a common line for storage capacitance connected to the storage capacitance, reference numeral 24 denotes a connecting portion short-circuiting between a gate line 2 and a source line 9, reference numeral 25 denotes a source side drive circuit which is a drive circuit provided on source lines side, reference numeral 27 denotes a terminal for applying electric voltage to a common line 4.
FIG. 20 is a plan view showing one pixel in a TFT array substrate in which channel etch type TFT is provided. FIGS. 21(a) to 21(f) are sectional views showing a manufacturing step for a portion taken along an F--F line shown in FIG. 20. In FIG. 20 and FIGS. 21(a) to 21(f), a reference numeral 1 denotes an insulating substrate made of an insulating material (transparent material can also be employed) such as glass, a reference numeral 3 denotes a gate electrode made of a metal material such as chrome or the like connected to a gate line 2, a reference numeral 4 denotes a common line made of a metal material such as chrome or the like formed on the insulating substrate 1, reference numeral 5 denotes a gate insulating film formed in such a manner that the gate insulating film covers a gate line 2, a gate electrode 3 and a common line 4, reference numeral 6 denotes a semiconductor layer made of semiconductor material such as non-doped amorphous silicon or the like formed through a gate insulating film 5 on a gate electrode 3, reference numeral 7 denotes a contact layer which is formed on the semiconductor layer 6 and is made of a semiconductor film such as silicon or the like doped with impurities such as phosphorus (P) or the like. One portion of the contact layer corresponding to the upper portion of the active area is removed by etching, so that the contact layer includes an etched-off region 8, and is divided into two areas shown by references 7a and 7b depending upon the etched-off region 8. Reference numeral 14 denotes a pixel electrode made of a transparent conductive film such as indium tin oxide (ITO) or the like. The pixel electrode is used to apply a driving voltage upon liquid crystal material. Reference numeral 10 denotes a source electrode formed on a contact layer 7a and connected with source line 9, reference numeral 11 denotes a drain electrode formed on the contact layer 7b, reference numeral 28 denotes a contact hole formed for electrically connecting a gate line 2 with a source line 9, reference numeral 29 denotes a passivation film made of silicon nitride or the like, for covering the whole of outer surface of TFT array substrate.
Manufacturing steps are described below.
As shown in FIG. 21(a), one of chrome (Cr), aluminum (Al), molybdenum (Mo), molybdenum-tungsten (Mo--W) or the like is deposited on insulating substrate 1. Then the deposited film is patterned by using a resist (photoresist) formed through photolithography process, in order to form gate line 2, gate electrode 3 and common line 4. As shown in FIG. 21(b), there are continuously formed a gate insulating film 5 composed of silicon nitride or the like, a semiconductor film such as amorphous silicon by, for example, a plasma CVD method. Also, when TFT is n-type TFT, n.sup.+ -amorphous silicon or the like in which impurities such as phosphorus are doped in high concentration by, for example, a plasma CVD method. Then, the semiconductor layer and contact layer on the semiconductor layer are patterned in order to form a semiconductor layer 6 and contact layer 7 in island like pattern by using a resist formed by photolithography process, by either dry etching method or wet etching method. As shown in FIG. 21(c), a transparent conductive film composed of ITO or the like is deposited. Then the transparent conductive film is patterned by photolithography process, in order to form pixel electrodes 14.
As shown in FIG. 21(d), a contact hole is provided in gate insulating film 5 on the gate line 2 in order to obtain a connecting portion 24 for connecting gate line 2 with source line 9. As shown in FIG. 21(e), one of Cr, Al, Mo, Mo--W, or the like is deposited. Then the deposited film is patterned by using a resist formed through photolithography process as a mask, in order to form source line 9, source electrode 10 and drain electrode 11.
Then, an etched-off region a recess 8 of the contact layer 7 is provided in order to remove contact layer 7 from channel area, by etching the contact layer 7 by using source electrode 6 and drain electrode 7 as masks. As shown in FIG. 2(f), a silicon nitride film is deposited by using source electrode 6 and the drain electrode 7 as masks by a plasma CVD method in order to form passivation film 29. Portions of passivation film 29 on the terminals of gate lines 2 and on the terminals of source lines are removed by using resists formed by a photolithography process, in order to provide connection portion to external circuit. The above-mentioned steps require six photolithography processes to form a TFT array substrate in which channel etch type TFTs are provided.
The functions are described below.
An electric voltage is applied through gate line 2 to gate electrode 3 to let TFT 21 be on state. Then, an image signal is inputted to source line 9; an electric current flows through source electrode 10, semiconductor film 6 and drain electrode 11. TFT 21 comprises source electrode 10, semiconductor film 6 and drain electrode 13. An electric voltage corresponding to the desired image signal is applied through pixel electrode 14 connected with drain electrode 11 to the liquid crystal material 22. A storage capacitance 23 is connected in order to prevent from variation of an electric voltage applied to the liquid crystal material under the influence of storage capacitance 23, corresponding to switching operation of TFT 21. The storage capacitance 23 is provided by common line 4, gate insulating film 5 and pixel electrode 14.
As shown in FIG. 18, gate line 2 and source line 9 are connected electrically at connecting portion 24 at the end portion of the TFT array substrate. This connection of gate line 2 and source line 9 prevents from breakage of TFT by high voltage to gate insulating film 5 caused by static electricity generated in manufacturing steps of TFT array substrate and in rubbing alignment films.
Conventional AMLCD in which channel etch type TFTs are provided is constructed in the above-mentioned manner. Six photolithography processes are required to form TFT array substrate. Thus there arises a problem that the manufacturing cost is high and the throughput is lowered.